Electrostatic discharge (ESD) causes substantial damage to integrated circuits during and after the chip manufacturing process. ESD events are particularly troublesome for CMOS chips because of their low power requirements and extreme sensitivity. On-chip ESD protection circuits for CMOS chips is essential. Generally, such circuits require a high failure threshold, a small layout size and a low RC delay so as to allow high speed applications. However, such ESD protection circuits have heretofore been difficult to design.
Previously, resistors and diodes were used in CMOS ESD protection circuits, but such resistors and diodes have been gradually replaced by 3-layer devices such as field-oxide MOSFETs, gate-oxide MOSFETs and parasitic NPN or PNP bipolar junction transistors in CMOS technologies. Others have used a parasitic 4-layer PNPN device known as a silicon control rectifier to protect the chip against the damages caused by ESD events.
Due to its high current sinking/sourcing capability, very low turn-on impedance, low power dissipation, and large physical volume for heat dissipation, parasitic lateral SCR devices have been recognized in the prior art as one of the most effective elements in CMOS on-chip ESD protection circuits. However, there is a major disadvantage when using the parasitic SCR device in ESD protection circuits in that the SCR device has a high trigger voltage. To perform ESD protection, the trigger voltage of an ESD protection circuit must be less than the voltage that can damage the input buffer or output driver. The typical trigger voltage of a parasitic lateral SCR device in the ESD protection circuits fabricated by the advanced 1 .mu.m CMOS process with highly doped drain and silicided diffusion is about 50 volts if the space from its anode to its cathode is 6 .mu.m.
Unfortunately, with such a high trigger voltage, the lateral SCR device cannot be used as the only protection element. FIGS. 1(a) and 1(b) illustrate an ESD protection circuit having an SCR structure. FIG. 1(a) illustrates the circuit diagram, while FIG. 1(b) illustrates the corresponding substrate. The ESD protection device illustrated in FIGS. 1(a) and 1(b) includes an SCR device 10 comprising cross-coupled bipolar PNP transistor 12 and NPN transistor 14 connected between an input/output pad 15, on the integrated circuit 16 to be protected, and the chip ground (also substrate) of the integrated circuit 16. The resistance R.sub.s of the P-substrate in which the SCR 10 is formed is illustrated along with the well resistance R.sub.w, which establishes a threshold current that must be reached before the SCR device 10 may be activated. As illustrated in FIGS. 1(a) and 1(b), an NMOS trigger FET 18 is further provided for lowering the triggering voltage of the SCR 10 to the breakdown voltage of the trigger FET 18.
The ESD protection circuit illustrated in FIGS. 1(a) and 1(b) thus requires that a trigger device such as NMOS trigger FET 18 be subjected to junction breakdown conditions before the SCR 10 may be activated. In particular, enough current must flow through the NMOS trigger FET 18 to initiate latchup by the SCR device 10. However, since the circuitry 16 being protected can also experience junction breakdown, there is no mechanism in the circuit of FIG. 1 to ensure that enough current will flow through the NMOS trigger FET 18 to initiate latchup. Furthermore, there is no assurance that device breakdown effects such as bipolar snapback will result in all the ESD current being absorbed by the ESD protection circuitry rather than the output circuit.
During operation of the circuit of FIG. 1, the NMOS trigger FET 18 operates in the junction breakdown condition to pull current through the well resistor R.sub.w. This breakdown voltage is approximately equal to the breakdown voltage of the circuitry to be protected, and, as just noted, it is impossible in such a circuit to ensure that the circuitry 16 to be protected will not conduct significant amounts of current due to device breakdown. It is also not possible to ensure that the circuitry 16 to be protected will not "steal" the current from the SCR device 10, thereby inhibiting the SCR 10 from latching up and absorbing the majority of the ESD event energy. FIG. 1 also shows a fixed resistor 17 used to limit current into the circuit to be protected. This fixed resistor has the disadvantage that it must be of a high value to prevent damage in a discharge event, but it must be of a low value to allow the circuit to properly drive a signal to the pad.
FIGS. 2(a) and 2(b) illustrate an ESD protection circuit of the type illustrated in FIG. 1 except that an NMOS FET 20 is added for lowering the breakdown voltage by floating the gate of NMOS trigger 18 when chip power V.sub.DD is low. FIG. 2(a) illustrates the circuit diagram, while FIG. 2(b) illustrates the corresponding substrate. As illustrated, the NMOS FET 20 is responsive to V.sub.DD to float the gate of the NMOS trigger FET 18 when the circuitry 16 to be protected is not powered up. Once powered up (V.sub.DD goes high) the gate of the trigger FET 18 is grounded so as to raise the breakdown voltage of trigger FET 18, thus minimizing the effect of the protection circuitry on the operation of the circuitry 16 to be protected. However, in the circuitry of FIGS. 2(a) and 2(b), latching by the SCR device 10 still relies upon the breakdown of the NMOS trigger FET 18 for initiation of latchup and is still susceptible to current "stealing" by the circuitry 16, which will also have floating gates. Thus, the aforementioned problems have not been overcome by the circuit of FIG. 2.
There is need in the art then for an ESD protection circuit which will enable the SCR to latch independent of the breakdown effects of the NMOS trigger FET. There is further need in the art for such a circuit that provides control over the amount of voltage necessary to initiate SCR latchup. The present invention meets these and other needs.